1. Field of the Invention
The present invention relates to an integrated circuit and method for testing memory on the integrated circuit.
2. Description of the Prior Art
It is becoming more and more common for integrated circuits to include embedded memory to allow rapid access to data by processing logic provided on the integrated circuit. As the use of embedded memory continues to increase, thorough testing and defect diagnosis has become a key requirement to ensure product quality and enhance product yield. Whilst embedded memory presents significant system performance and cost reduction advantages, it brings its own testing issues. Externally generated test vector style tests are not suitable for verifying embedded memory arrays for a number of reasons. Firstly, the time spent in the manufacturing test grows exponentially as the embedded memory die area increases, which often makes such test vector style testing too costly. Furthermore, it is sometimes not possible to create a set of vectors that can detect all possible types of memory defect.
A known technique which alleviates such problems is to provide the integrated circuit with a memory Built In Self-Test (BIST) controller. In simplistic terms, a memory BIST controller is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the embedded memory. These tests can be executed at the design's full operating frequency to prove the memory operations and identify errors caused by silicon defects.
In accordance with one known technique, a separate BIST controller is provided for each embedded memory within the integrated circuit. However, as the number of memory circuits provided within the integrated circuit increases, such an approach results in the chip area devoted to testing becoming unacceptably large. Hence, techniques have been developed which enable the BIST controller to be shared amongst several embedded memories within the integrated circuit. One such technique is described in U.S. Pat. No. 4,969,148, where, as for example shown in FIGS. 6 and 7 of that document, a single controller is shared between a number of embedded RAM (Random Access Memory) blocks within the integrated circuit. As can be seen from those figures, this technique involves providing a two-input multiplexer assembly in association with the data in port of each RAM block.
In the example of FIG. 6 of U.S. Pat. No. 4,969,148, the RAM blocks are connected in a daisy chain arrangement, such that the data input line of RAM 1 is connected to the serial data out port of the controller, the data output line of RAM 1 is connected to the data input line of RAM 2, the data output line of RAM 2 is connected to the data input line of RAM 3 and the data output line of RAM 3 is connected to the serial data in port of the controller. When in the test mode, the controller can operate at the system clock speed and serially shifts test bits from its serial data out port through the sequence of RAM blocks via the associated multiplexer assemblies, with the output from the last RAM block being returned to the serial data in port of the controller. During this test process, the same address is provided to each of the RAM blocks in parallel. This arrangement for sharing the test circuitry simplifies the testing procedure since the three memories are treated as if they were one large memory. In accordance with an alternative embodiment shown in FIG. 7 of U.S. Pat. No. 4,969,148, a RAM select counter and associated “1 of 3” multiplexer is used to provide an arrangement where only one of the memories is tested at a time.
U.S. Pat. No. 6,191,603 describes a modular embedded test system for use in integrated circuits. In accordance with this technique, a number of core modules are provided, and each core may possess BIST functions which can be activated using external commands. An access scan chain is provided for controlling tests performed on each core, and a separate data scan chain is provided to apply specific test vectors and observe their responses.
The article “An Effective Distributed BIST Architecture for RAMs” by M Bodoni et al, Proceedings of the IEEE European Test Workshop (ETW '00), describes a BIST architecture employing a single BIST processor used to test all the memories of the system, and a wrapper for each SRAM including standard memory BIST modules. The architecture employs a normal test scan chain (NTScan) and a results scan chain (Resscan), and commands for these two scan chains, along with synchronisation signals used to forward test primitives to the wrappers, are multiplexed within each wrapper to reduce routing overhead. March tests (or test algorithms) are applied one memory operation at a time, and as a result multiple operations cannot be applied at system clock speed.
As the number of memory units embedded within the integrated circuit increases, then this results in an increase in the complexity of the interface between those memory units and a shared BIST controller for those memory units. The known BIST controller sharing techniques become complex to manage as the number of memory units increase, and further lack flexibility with regard to the tests to be applied on each of the memory units.
It would be desirable to provide a technique which provided a communication scheme between the controller and an arbitrary number of associated memory units, which allowed those multiple memory units to be tested in parallel at operating frequency, with the communication scheme being readily able to cope with increased numbers of memory units, and providing a flexible approach for organising the tests to be performed.